EE3621 To enhance understanding of VHDL-based system design, testing, and implementation.

Embedded Systems

Assessment - Design and implementation of sequence detector on FPGA

Objectives:

To enhance understanding of VHDL-based system design, testing, and implementation.
To enhance understanding of state machines.
To introduce the need for debouncing in practical system implementations.
To enhance student competence is presenting complex technical material.

Brief Description of the assessment:

The main task in the group project is to implement a sequence detector using the NEXYS FPGA board, which will be used for the prototyping and testing of the implemented system. Design will take place from scratch, i.e., VHDL code will have to be written, synthesized, debugged, analysed and subsequently used for the programming of the FPGA board. Debouncing strategies will have to be considered as well as power consumption issues.

The students are required to:
Use Xilinx Vivado in order to design their system, implement a clock divider in their system and show graphs with the signals that are used by their system.

Produce a bit file and verify the operation of their system using simulation

Present an analysis of the state machine that they propose for their system and explain its suitability for the task in hand.

Consider debouncing strategies for dealing with bouncing issues and propose a suitable strategy. Show that they can use Vivado in order to estimate power consumption.

Learning outcome 1: Design systems using VHDL using a suitable design interface.
Learning outcome 2: Implement systems on FPGA Design state machines
Learning outcome 3: Understand the effect of bouncing and implement effective debouncing strategies.
Learning outcome 4: Estimate power consumption of a design.

Project report
The project report should be properly presented and should include suitable interpretations and conclusions.
Project report will assess:
Understanding of the competing design choices in embedded system design
Competence in deploying VHDL for the description of hardware/circuits
Knowledge and understanding of how to compute consumed power
Application of relevant laboratory skills to embedded system design

Submit a laboratory report that clearly reports the lab work undertaken towards the exercises set out in the assignment brief and providing conclusions and interpretations on the work done.
Present work undertaken orally and answer relevant questions following the presentation.
Demonstrate the operation of the developed system and answer relevant questions following the demonstration

Title: Design and implementation of sequence detector on FPGA.

Sequence detectors are very important in a variety of applications. The main objective of this group project is to implement a sequence detector for FPGAs. The NEXYS FPGA board will be used for the prototyping and testing of the implemented system (see board schematic on the next page). You are asked to take the steps below for your implementation and presentation:

Using Vivado, write VHDL code for the implementation of a sequence detector in VHDL using push buttons. Four push buttons should be used for entering symbols (‘1`,`2`,`3`,`4`). Further, the push button in the middle should be used for initialisation.

Up to 10 symbols could be entered after pressing the initialisation push button. When the sequence "4 3 1 2 3" is entered, then the LEDs should start flashing. Please note that the right sequence of symbols need not necessarily be entered immediately after the initialisation push button is pressed. For example, the sequence "2 4 1 2 3 4 3 1 2 3" should be able to activate the flashing of the LEDs.If 10 symbols have been entered but the right sequence of symbols has not appeared yet, then the system should lock and the LEDs should show the following predefined pattern: on, off, on, off, on, off, on, off, on, off, on, off.If the system is locked, the user will need to press the initialisation button in order to be allowed to start entering new symbols.Synthesise and implement your design (in your report present the RTL and technology schematics).Analyse the code (produce summary) and give a brief description of your implementation.Use simulation to test your design and display input/output results with a brief description.Generate bit-stream.Use Vivado to estimate power consumption estimates for your design. Show this estimate in your report.

NOTE: In some cases pushing a push-button will not trigger the expected response in your system. This may be due to the fact that in many cases, pushing a push-button does not create a clean transition from 0 to 1. Instead, the input may bounce back to zero and back to 1 within a very short period of time. In order to deal with this problem, you can try using a low clock frequency. But in general you can debounce the pushbuttons in your design by ensuring that the input is considered to be equal to 1 only after it has remained so for a predefined number of clock cycles.